The present invention relates to a semiconductor memory device, and more particularly, to a self refresh operation of a semiconductor memory device.
In general, a memory cell in a semiconductor memory device is configured with a transistor acting as a switch and a capacitor storing charges (data) therein. Depending on whether charges are stored in the capacitor of the memory cell, i.e., depending on whether a terminal voltage of the capacitor is high or low, data value is determined as ‘HIGH’ (logic 1) or ‘LOW’ (logic 0).
Since data retention is a state that charges are accumulated in the capacitor, there is no power consumption in principle. However, charges, which are initially stored, may disappear due to leakage current caused by a PN junction of a metal oxide semiconductor (MOS) transistor, which may lead to data loss. To prevent the data loss, data in the memory cell are read before the data are lost, and charges must be then recharged according to the read data.
Data can be retained through periodic repetition of such operation. This recharging process of cell charges is referred to as a refresh operation. Thus, a semiconductor memory device consumes refresh power due to this refresh operation. It is very important to reduce power consumption in a battery-operated system requiring low-power performance, which is a critical issue.
One of various attempts to reduce power consumption in the refresh operation is to change a refresh period according to temperature. In the semiconductor memory device, data retention time becomes longer as the temperature becomes lower. Therefore, the power consumption can be reduced by dividing a temperature range into a plurality of sub-ranges and relatively reducing a refresh clock frequency at a low temperature range. Thus, an internal temperature of the semiconductor memory device is detected, and a self refresh period is adjusted such that the semiconductor memory device itself performs the refresh operation according to the detected temperature.
FIG. 1 is a block diagram illustrating an on die thermal sensor (ODTS), a control signal generator, and a self refresh oscillator of a conventional semiconductor memory device.
The ODTS 15 detects an internal temperature of the semiconductor memory device to output a thermal code containing temperature information.
Specifically, a bandgap unit 10 detects a temperature using the fact that the change in a base-emitter voltage (VBE) of a bipolar junction transistor (BJT) is about −1.8 mV/° C. in bandgap circuits which are not influenced by the change of temperature or power supply voltage. The bandgap unit 10 outputs a first voltage VTEMP corresponding to the temperature by 1:1 by amplifying the finely changing base-emitter voltage (VBE) of the BJT. That is, as the temperature of the semiconductor device becomes higher, the bandgap unit 10 outputs a lower base-emitter voltage (VBE) of the BJT.
An analog-to-digital converter (ADC) 20 coverts the first voltage VTEMP in analog form outputted from the bandgap unit 10 to a thermal code in digital form. Generally, a tracking analog-to-digital converter is most widely used as the ADC 20.
The tracking ADC tracks the first voltage VTEMP using a second voltage in the tracking ADC itself to thereby generate the thermal code, which will be described below. First, voltage levels of the first voltage VTEMP and the second voltage are compared with each other, and the thermal code is increased or decreased according to the comparison result. At this point, the voltage level of the second voltage is also increased or decreased. The increased or decreased second voltage is compared with the first voltage VTEMP again. By repeating the above procedure, the second voltage tracks the first voltage VTEMP, and thus the thermal code corresponding to the first voltage VTEMP is generated.
In summary, when the bandgap unit 10 outputs the first voltage VTEMP containing temperature information, the ADC 20 converts the first voltage VTEMP to the thermal code containing temperature information.
The thermal code outputted from the ODTS 15 is transmitted to a control signal generator 30, and the control signal generator 30 then generates a self refresh control signal TRIP_POINT_FLAG. The self refresh control signal TRIP_POINT_FLAG includes flag signals which are activated at a predetermined temperature or higher. Referring to FIG. 2, as temperature increases, a TEMPA signal is activated first, and thereafter TEMPB and TEMPC signals are respectively activated at corresponding detection temperatures in sequence.
The self refresh control signal TRIP_POINT_FLAG, which contains the TEMPA, TEMPB and TEMPC signals, indicates the temperature of the semiconductor memory device. When the TEMPA, TEMPB and TEMPC signals are all logic low levels, the semiconductor memory device is in the, lowest temperature range. When the TEMPA signal is a logic high level but both the TEMPB and TEMPC signals are logic low levels, the semiconductor memory device is in the second lowest temperature range. When the TEMPA, TEMPB and TEMPC signals are all logic high levels, the semiconductor memory device is in the highest temperature range. That is, the self refresh control signal TRIP_POINT_FLAG containing the TEMPA, TEMPB and TEMPC signals indicates which temperature range the semiconductor memory device is in. The self refresh control signal TRIP_POINT_FLAG containing the TEMPA, TEMPB and TEMPC signals is illustrated in FIG. 2.
A self refresh oscillator 40 receives the self refresh control signal TRIP_POINT_FLAG to generate an oscillating periodic wave OSC, thereby controlling a self refresh period of the semiconductor memory device. As described above, since a data retention time in a memory cell of the semiconductor memory device decreases as the temperature increases, the self refresh period becomes shorter as the temperature is higher.
The self refresh period controlled by the self refresh oscillator 40 will be more fully illustrated with reference to FIG. 2. The self refresh period increases by 5% in a section (5% inc) where the TEMPA is a logic high level and both the TEMPB and TEMPC signals are logic low levels, based on the self refresh period of a section (1x) where the TEMPA and TEMPB signals are logic high levels and the TEMPC is a logic low level. Furthermore, the self refresh period increases by 15% in a section (15% inc) where the TEMPA, TEMPB and TEMPC signals are all logic low levels. On the contrary, the self refresh period decreases by half in a section (2x) where the TEMPA, TEMB and TEMPC signals are all logic high levels, i.e., a section where the semiconductor memory device is in high temperature range. Herein, the reference symbol ‘2x’ means that the self refresh period is reduced to half so that the self refresh operation is performed two times more in the high temperature section (2x) than the normal section (1x).
To summarize overall operation, the ODTS 15 measures the internal temperature of the semiconductor memory device to output the thermal code, and the control signal generator 30 then outputs the self refresh control signal TRIP_POINT_FLAG containing the TEMPA, TEMPB, TEMPC signals and the like, which indicate corresponding temperature ranges. The self refresh oscillator 40 controls the self refresh period of the semiconductor memory device depending on the section indicated by the self refresh control signal TRIP_POINT_FLAG.
As described above, the semiconductor memory device controls its self refresh period according to the temperature variation. However, in case that the temperature continuously changes near a specific temperature, for example, in case that the temperature continuously changes near a temperature at which the TEMPC signal is activated, the self refresh period of the semiconductor memory device abruptly changes into the self refresh period corresponding to the sections 1x, 2x, etc, causing the unstable operation of the semiconductor memory device after all.